Algebraic magnitude comparators



2 sheets-sheet 1 R.l R. JOHNSON ALGEBRAIC MAGNITUDE COMPARATORS oct. s, 1959 Filed lay 18, 1954 R. R. JOHNSON ALCEBRAIC MAGNITUDE (JOMPARIVTOl-Sl Oct. 6, 1959 2 Sheets-Sheet 2 Fileanay 18, 1954 .l

2,907,871 ALGEBRAIC MAGNITUDE coMPARAroRs Application May 18, V1954, Seal N0.- 430,531

19 Claims. (Cl. 250-27) .Thisinvention relates to algebraic magnitude comparators, and more particularly to algebraic magnitude comparators for determining and indicating the relative magnitudes of two algebraic numbers by comparing the relative magnitudes of the corresponding digit and sign signals of the two numbers in an integrated operation.

Algebraic comparators as contemplated by the present invention are devices which are adapted to indicate the relative magnitudes of numbers where the signs of the numbers are considered as weighting factors. Thus, where algebraic numbers are of diiferent signs, the algebraic comparator indicates that the positive number is the greater. And, if both numbers are'negative the algebraic ,comparator indicates that the negativenumber yhai/'ing the smaller absolute magnitude is the greater.

An algebraic vcomparator offthis type is particularly useful .in obtaining the solution of, many important economic,v scientific, and purely mathematic problems. For example, Sucha comparator may be utilized in linear .approximations utilizing the simplex method. In programming ,a computer for calculations according to the simplex l'nCthod, pairs of algebraic numbers must be '.ompared ,fOr their relative algebraic magnitudes as part of .the .solutional program- In the `past the direct comparison and indication of -the relative magnitudes of `two numbers has been limited to the comparison of the absolute magnitude of the numbers, no provision being made for the direct algebraic comparison of both positive and negative numbers. tudes of numbers has been Ato subtract one of the numbers from the other, and to determine their relative United States vPatent O One method of .comparing the absolute magni- 0 absolute magnitudes asla function'of the sign of the i differences resulting thereby. An alternative method, .which Ais :somewhat similar to -this method, is to -add Vthe complement Lof `one of the vnumbers to the other, the relative absolute magnitude then being indicated by the sign or sense of the sum. Both of these methods require an adder or subtracter circuituas well as an output element or indicating device.

An improved V,circuit for determining the" relative absolute magnitude of two numbers is disclosed in copending U.S. patent application Serial No. 394,441 entitled Electronic MagnitudeComparator by Robert Royce Johnson, iiled December l0, 1953. The basic principle of the Johnson'comparator is that the relative absolute magnitudes .of two numbers is Ydependent upon :the relative absolute magnitudesof .the most l.significant dissimilar corresponding digits of the two numbers. `In the Johnson comparator, the corresponding binary digit signals of the two numbers vare compared and the sense of theprnost .significant-corresponding dissimilar digital comparison .placed in a bistable :storage element; the

stateof the bistableelement at the termination of the comparison indicating the ,relative absolute `nlargnituies of the two numbers. 'i

IIn utilizing the available prior art absolute magnitude comparison circuits, it is necessary to perform separate Vlarly noticeable yin ,the eld of serial comparison.

lCC

operations to determine the relative absolute magnitude of the number and the relative sign magnitude v"of Athe numbers. Thus, where the addition or subtraction method is followed it .is possible w @bain an algebraic, comparison by utiliaing'the adder or subtracte'r and then analyzing the signs of the numbers may be stored in separate bistable elements. AThe results of theseiwooperations may .than be compared inail. pile put circuit which is additional structureinthe computer, This methodof obtaining algebraic comparison is unnecessarily complicated and introduces cert in delaysl in obtaining the nal comparison signal which may undesirable. l

The present invention `overcomes the above and other disadvantages of ,utilizing separate prior art absolute magnitude comparators and sign storage devises by pro,- viding a class of 'algebraic comparators may simply mechanized in the form of a single gating matrii. Thus, parallel cgmparators are provided by present invention wherein a signal indicating the relative u N.- braic magnitude of two numbers is produced ina` single gating matrix. VIn a similar manner, serial comparators are provided wherein a very simple gating circuit utilized to directly ,enter algebraic comparison Asignals into a bistable element. 'j

yIn its basic structural form, the present invention eemp'ris'esa logically mechanized gating matrix including a iirSI gating circuit which Produces an ,outputfsignal'Cn indicating the relative` absolute magnitude of AiIylput num.- bers A and B, and a 4second gating `circuit .responl iye to signal Cn and :to signals Sa and S b,"respectively indicating the signs ofgA and B, and directly producing ra lsignal Ca indicating the relative algebraic magnitude of the numbers A and B. i, While manyV methods are known for vrepresenting y algebraic numbers, only two are considered in the present specification in order to illustrate two corresponding classes of the invention. According to one method, ,each algbraic number is represented by its absolute tilde plus a sign digit having a value for 0 @11.14.41 9F positive and VAnegative numbers, respectively. This algebl is representation iS heitillaite? reffffsd t0 aS Qlutefmagnitude representation Sif'eral nflthsdnsf comparing 'alf'.rebraic numbers represented 1.as ,signabsolute-,magnitudes are provided by the .present yi p. tion; vthe methods varying accordingf-tothe partlcular vpreseiitatiui Lof the numbers. The .numhersrnay ehe presentedin parallel, for example, or V1serially.with the least significant digit lfirst or most .significantv digitfirst.

Another method of representing algebraic .nuiiibegrlsiis to represent negative numbers ascqmplementswhere -a complement :corresponds .to Ethe digital ,representation v.of the Vresult when the number lis `'subtracted from zero.

`The contribution -of lthe present ginventionis .particuwill be shown that extremely.simple algebraicserial comparators may be obtained according 'to prineiples des'cribedbelow.

Accordingly it is an yobject vof ,the present .inyentinn to provide an algebraic vcomparator Afor directly4 determining and .indicating the relative magnitudes .of we .algebraic numbers. l f n Another .Object of the .investiga ils .t0 provisie analgebraic comparator for-*indicating .the-relative' magni de Aof algebraic numbers ,whichregui'res on yna vs .e lga i g matrix, obviating the necessity of an adderA or subtracter and additional bistable elements for storing signs of the numbers.

A further object of the invention is to provide an algebraic comparator for determining `and indicating the relative magnitude of numbers in a sign-absolute-magnitude representation.

Yet another object of the invention is to provide an algebraic comparator for determining and indicating the relative magnitude of numbers in a complemented-magnitude representation.

A still further object of the invention is to provide parallel algebraic comparators for indicating the relative algebraic magnitude of numbers in a single gating matrix.

An additional object of the invention is to provide serial algebraic cornparators for indicating the relative magnitude of algebraic numbers, the comparator requiring a simple gating circuit for entering signals into a bistable element.

The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings in which several embodiments of the invention are illustrated by way of examples. It is to be expressly understood, however, that the drawings are for the ptupose of illustration and description only, and are not intended as a definition of the limits of the invention.

Fig. l is a block diagram of an algebraic comparator according to the present invention;

Fig. 2 is a schematic diagram of a parallel algebraic comparator for comparing and indicating the relative y magnitude of two algebraic numbers, each number being represented as an absolute magnitude and sign;

Fig. 3 is a schematic diagram of a serial algebraic comparator, deiined by the same basic functions as the comparator of Fig. 2, wherein the numbers are represented by signals serially received in the order of the least significant numerical digits irst and sign last;

Fig. 4 is a schematic diagram of a parallel algebraic comparator for comparing and indicating the relative magnitudes of two algebraic numbers, each negative number being represented by its complement; and

Fig. 5 is a schematic diagram of a serial algebraic comparator, defined by the same basic functions as the comparator of Fig. 4, where the numbers are represented by signals serially received in the order of the least significant numerical digits last and sign iirst.

Reference is now made to Fig. l wherein there is shown a block diagram of the basic structural form of an algebraic comparator according to the present invention. As shown in Fig. l, comparator circuit 10 includes an absolute magnitude'comparison circuit ltlCn which responds to `input signals representing numbers A and B and produces an output signal Cn indicating the relative absolute magnitudes of numbers A and B. The signal Cn may be considered to be the nth or last comparison in `a series of absolute magnitude comparisons in the Various digit positions. In addition, comparator '10 also includes an algebraic magnitude comparison circuit ltlCa which receives signal Cn and sign indicating signals Sa and Sb produced by a source 1l and produces output signals which may be utilized to actuate lan output element 12 to produce a comparison signal Ca indicating the relative lalgebraic magnitudes of numbers A and B.

lIt should be understood at the outset, however, that output' element 12 is utilized in conjunction with comparator 10 only where the comparator of the present invention is adapted to receive the input signals representing numbers A and B in a serial fashion. As will become apparent from the ensuing discussion, where the input signals representing numbers A and B are received 'by comparator 10 in a parallel fashion, ie., all input signals of numbers A and B received simultaneously, output element 12. is eliminated and the output signals produced by comparator 10 directly represent signal Ca.

Before describing the specific forms of algebraic comparators which are defined by the present invention and illustrated in the generic block diagram of Fig. l, it is helpful to first introduce the basic concepts of the present invention relating to a novel method of comparing algebraic numbers expressed as binary digits.

The relative numerical magnitude, disregarding the signs, of two numbers represented by two sets of weighted binary digits, is a function of the relative magnitudes of the corresponding binary digits representing the two numbers. For purposes of this discussion, it is assumed at the outset that a binary l represents a greater digit mag nitude than a binary 0, expressed by the absence and presence, respectively, of a bar over the binary digit symbol. Letting the subscript j represent a binary-digit position the relative magnitudes of two corresponding binary digits of numbers A and B, respectively, may then be expressed as:

where the dot represents the logical and and the plus the logical or according to the principles of Boolean logic. v

For discussion purposes, it may be assumed that the corresponding numerical digits of numbers A and B are considered in the order of ascending signiicance and that the binary digits representing each numerical digit are considered in the order of ascending weights. The relative numerical magnitudes of the two numbers is dependent upon the relative magnitudes of the most 51gnicant dissimilar corresponding binary digits compared. Let it be assumed that the result of the numerical magnitude comparison process is represented by a binary signal Cn having a l-representing level when the aggregate of the binary digits compared indicate-s ltl1at A is greater than B and having a O-representing statelf' the aggregate indicates that A is less `than or equal to B. Thus, the value of signal Cn indicates the relative numerical magnitudes of numbers A and B in the following manner:

If A B, then Cn=l If A B, then Cn=0 1f l4:15', then cn=0 The value Cj, of Cn at any binary digit place, as a function of the vbinary digits in the binary digital place and the value Cj 1 of Cn in the preceding binary place, may then be derived from the following truth table.

Table l Ai Bi Ci-i C.

`and vsignbinary signals Sa; and Sb,

A vand B may be expressed vas a function Ca of the relative'. numerical magnitude Cn and the signs of the numbers, Sa and Sb. For example, if both numbers are negative, vthe number having the lesser numericalv magnitude has the greater true algebraic magnitude. Similarly, if one is positive and the other negative, the positive number is algebraically the larger.

The true algebraic relative magnitudes of numbers A and B,i'covering all possible conditions, may be represented in a truth table, such as Table II below, where it is assumed that thesign comparison is performed as a function of the total relative numerical magnitudes of A and B. In the table, Cn represents the results of the numerical comparisons or the 11th comparison, Sa and- Sb represent the algebraic sign of numbers'A and B, respectively, and Ca represents the true algebraic relation of numbers A and B as a function of Cn, Sa, and Sb.

Numerical magnitude comparison signalfCnhas a binaryA 1 value when the numerical magnitude of A is greater than the numerical magnitude of B, and has a binary 0 value when the numerical magnitude of A is less than or equal to'the' magnitude of Bf' In accordance with convention, a positive and a negati-ve algebraic sign is represented by a O-representing and a 1-representing sign signal, respectively. Thus signy representing signal Sa has a binary 0 value when input number A is positive, and has a binary l value WhenA is negative. Similarly, Sign representing signal Sb has values of 0 and l, respectively, when input number B is positive and negative. vxIn the table, Ca has a binary 1 value when the true algebraic magnitude of v A is greater than the true algebraic magnitude of B, and a binary 0 value when the true algebraic magnitude of A is less than or equal to the algebraic magnitude of B.

y ,TableII sa sb 'on oa o o o o o 1 o v 1 1 o o o From Table II, the function for Ca may be written: (ZCVa) un u Crz=Cn.S'a-{-n.Sb i wherezCn represents the Value o'f'CJ- in the nth' digit place Referring now to Fig. 2, there is shown a .parallel algebraic comparator 20 mechanized according to the above principles for comparing two algebraic numbers A and B, represented by numerical binary signals A1,..Aj,...Anand1,...j,..

` respectively. As shown-in Fig. 2, the comparator 20 comprises an absolute magnitude comparison circuit 20Cn and an algebraic magnitude comparison circuit 20Ca., The absolute magnitude comparison circuit 20Cn produces a yrelative nuv merical magnitude Vsignal Cn in response t'o the numerical vbinary signals A1, Aj, Amand B1, Bj,

' En and the algebraic magnitude vcomparison circuit .20Ca, in response to the numerical magnitude fsignal 'Cir and the sign signals Sa'. and Sb, lproduces a binary signal Ca Bn; respectively,

representing the relativemagnitudes of vnumbers A and B. 1

The absolute magnitude compari'son'circuit ZCn may be considered as including n logical gating circuits,

2Min-'#1,'. 20Cn-i, -.`20Cn-z, where n represents the number of numerical binary digit places in *each of jtheralgebraic numbers A vand B.A Each of the above logical gating circuits may bel rnechanized'in accordance lwith the logical expression (20Cn) derived above, Jwhich bestored in a storage element,

It is evident that the logical expressions 'for each yof the logical gating circuits included in the comparison circuit 2001 are similar with the exception of the logical expression forthe ZOCm-l gating circuit, which is mechanized in accordance with the expression:

where the Cj 1 term is nonexistent.

The algebraic magnitude comparison circuit 20Ca vf or producing the Ca signal is mechanized in accordance With the llogical expression (20Ca) derived above.,v In order to provide the complementary signal Cn required in the;

above expression, a` level complementing circuit ZOQal is provided inthe algebraic comparison circuitl 2 0Ca.

Each of the and functions in thelabove equations is provided in Fig. 2 with van fand" circuit which responds to signals applied to separate input terminals and kproduces l-representing output signals only when all input signals are lerepresenting signals. Thus, the and function CrLSa in the mechanizing function -(20Ca) above is'fp'rovided with an an 7 circuit 20Ca.-2 in the logical gating circuit 20Cz of Fig.l2, which. respondswto signals Cn and Saand produces a l-representingoutput .signal when both Cn andSa are l-representing signals. Similarly the and?` circuit Ca-3 responds toA separately applied input signals to produce l-representing output signals deined by the'corresponding and function in Equation 20C@ above. 1

Each of the or functions. in Vthe above equation is provided by an or circuit responding to separately-applied input signals for producing a l-representing output signal when any one or more of the input signals-is'in a 1-representing state.. Thus, Athe orfunction Cfif1+n5b of Equation 20Ca above is provided with anor, circuit 20Ca-4 inthe algebraic magnitude compar'son circuit 20Ca of Fig. 2, which responds to separatelyapplied input signals Cnna and @n.Sb and producesra l-representing output signal Ca when either one or both.. of the input signals is a l-representing signal.

It is evident from themanner employed-r in deriving the general function (ZOCa) from Table Il above, that the function for Ca is independent of' themanneremployed foridetermining the values of the individual terms Cn, n, Sa, and Sb., For example, the relative'numerical magnitudes ofthe numbers 'A-and'B, represented by signal Cn, may be obtained; byv either a parallel or serial comparison of the corresponding numerical lbinary digits.

If the corresponding numerical binari/digits are serially l compared in the order of ascending-Weights or significants',gthen the lvalue of Cj, representing theft-value of Ci=Af-BflCi1 FiBD previously derived from Table I above. Since the above expression requires the value Cj 1 ofCn-in the preceding pl'acethe value of 'Cj for each binary digit place `must such as -a ilip-ilop,="for one binary`digit time interval; If the; sign signalsrSa .and Sbof the expression (20Go) above' yare yreceived after the yiinal value, Cn, of Cj is determined and stored inthe storage element, then thevalue for Cn will beavailablefrom the storage element at the'same, timethat Vthe sign signals Sa and Sb are available..

Referring now to Fig. 3 there is shown a serial algebraic comparator 30 mechanized according to the above principles for comparing algebraic numbers A and B represented by two sets of numerical complementary binary signals A, and B, respectively, and sign signals Sa' and Sb, respectively; each of the algebraic numbers being received in the order of least significant numerical digit first and sign last, and negative numbers being represented by their absolute magnitudes and negative signs. As shown in Fig. 3, the `algebraic comparator circuit 30 is comprised of an absolute magnitude comparison circuit 30Cn and an algebraic comparison circuit 30Ca. 'As shown in the figure, the absolute magnitude circuit 30Cn produces a pair of numerical comparison signals representing the value of Cn, in response to the A, A, B, and signals and a binary signal s which is in a 1- representing state during reception of numerical digit signals and in a O-representing state during reception of the sign signals. The algebraic circuit 30Ca, in response to the numerical comparison signals, a reset signal R, clock pulses Cp, and the sign signals Sa and Sb, produces a pair of binary control signals llCa and Ca, respectively, representing Ca.

It is noted that the output element 12 of Fig. 1 is a ip-op Ca having separate l and 0 input circuits responsive to the binary control signals lCa and 0Ca, respectively. Therefore before considering the specific mechanization of the logical circuits 30Cn and 30Ca of Fig. 3, it is necessary to consider the general form of equations defining the input functions for ip-flops. The discussion here is brief since the theory of flip-flop control functions is discussed in considerable detail in copending U.S. patent applications Se 'al No. 327,567 for Binary- Coded Flip-Flop Counters by Eldred C. Nelson, filed December 23, 1952, now Patent No. 2,816,223, and Serial No. 327,131 for Binary-Coded Flip-Flop Counters by Robert Royce Johnson, filed December 20, 1952, now Patent No. 2,853,238.y Although flip-flop C of Fig. 3 is represented as a conventional nip-flop having 1 and 0 input circuits, such that pulses applied to the l and 0 circuits set the flip-flop to the land 0 states, respectively, it should be understood that, by a slight alteration of the algebraic circuit 30Ca, other types of flip-flops may be used, such as an overriding flip-flop, which is set to its O-representing state during each binary digit time interval when a pulse is not applied to the l input circuit.

As is more fully explained in the above copending applications, three general types of flip-nop input functions may be utilized to control the sequence of stable states of an associated flip-flop. According to one type of equation, the sequence of stable states of the Hip-flop is directly defined so that the value of the equation (1 or 0) at a particular time indicates the next flip-flopsetting. This type of function may be referred to as a setting function. When a setting function is utilized, the flip-op must be an overriding flip-flop of the type just described, or a complementer circuit must be introduced to translate the gating output signal into complementary signals.

According to a second type of defining equation, the conditions for changing the flip-flop stable state, or triggering the flip-flop, are established. When this type of mechanization is utilized, a conventional flip-flop is employed and the gating circuit signal is applied to both the 1 and 0 input circuits of the flip-flop. In many situations, the changing type of equation may be separated into two partial-changing functions, separately defining the conditions for changing the associated flipfiop stable state from O to 1 and from 1 to 0. The partial-changing functions are particularly useful where the equations include the output signals of the flip-flop to -be controlled. In this case, the partial-changing functions may be simplified according to rules briefly considered below which are fully described in the abovementioned copending applications to Nelson and lohnson. The setting, changing,s and simplified partialchanging functions for controlling a flip-flop Fk (k representing any flip-flop) are designated, respectively, by the notations: toFk=; 1Fk=0Fk=; and 1Fk=, 0Fk=.

As is more fully explained in the above-mentioned copending applications to Nelson and Johnson, any ipop function may be written in the form:

Fk and 171k representing the complementary output signals of flip-flop Fk. This may be reduced to the simplified partial-changing functions:

G and H being any functions of variables other than Fk and I tk.

Since the absolute magnitude comparison of numbers A and B is performed before the signs are compared, the absolute magnitude comparison and the algebraic or sign comparison may be considered as two separate, consecutive processes, i.e., an absolute magnitude comparison process followed by an algebraic comparison process. Thus the expression (20Cn) derived from Table II above may be modied, by including the binary signal 13s as an and function, to form a numerical or absolute magnitude comparison function as:

Cj:PS[7'.j-iCj 1.(Aj|-)] Where the iinal value for Cj at the termination .of the numerical comparison represents the value for Cn.

The algebraic or sign comparison of the numbers A and B may then be expressed in accordance with the general function (20Ca) above derived from Table II as a function of the result Cn of the numerical comparison and the algebraic signs of the numbers indicated by the sign signals Sa and Sb. By substituting the term C, 1 for Cn, 1 for n in the expression for Ca, and including the binary signal Ps as an and function, the algebraic comparison function becomes:

PS.(C7 1.gI-i 1j) Since the numerical comparison of the numbers A and B is completed before the sign or algebraic comparison is performed, the above numerical and algebraic comparison functions may be logically added to form a setting function for flip-flop Ca as follows:

+PS.(C7' 1.AKj-i-j 1.Bj) =Cj 1.[PS.(7-iB7-)+PS-j] 'i |j 1[PS.A7-.j+PS-Bj] where the complementary lsignals Ps and 15s are added to identify the sign and numerical binary signals, respectively. The above setting function may be Written in the form of simplified partial-changing functions as:

' the numbers.

9 sign signals Sa `and :Sb 'fareseparately generated bya sign signal Icircuit 311 mechanized according to the functions:

Vderived when the number is subtracted from zero, a general function for Cav may be lderived from lTable III belowfwhere -the valuesofCa for all possible combinations of Cn,` Sa, and Sb Aare presented.

Table III Sa Sb Gn Ca V0 0 0 y(l 1 0 1 -1 0 0 0 1 1 0 0 0 0 1 1 o V1 1 1 l 0 '1 0 1. 1 1 1 1 Table III was derived in thevfollowingK manner. All possible combinationsof values forv Sa `and Sb are rst written under their respective `columns,ri.e., 00,;0-1, l0, and 4l1. A zero is then inserted -in the Cn column for each -of the above combinations of values. Values of O0, 01, 10, and 1'1 `for Sa and Sb are then repeated in the same vorder and a 1 inserted in the Cn column opposite each repeated combination. In this manner all possible combinations of values and Cn Vare included in the table.' The correct value for Ca is then determined for each combination of variables Sa, Sb, and Cn,.and inserted in the Ca column in the corresponding row' of.l the table. This is accomplishedby first inserting the same value in the Ca column as in the Cn column for each yrow wherein both numbers A and B are positive numbers. This is permissible be'- cause the algebraic relative magnitude of two positive numbers -is equal to the numerical relative magnitude of Thus Ca is equal to Cdn when both Sa and Sb have values of 0, i.e., Ca is equal to 0 when Sa, Sb, andl Cn are:` when Sa and Sb are both 0 and Cn is equal to 1.

As betweentwo numbers having different signs, the

'positive number has a relative algebraic magnitude greatd for variables Sa, Sb,

each equal to 0, and vCa is equal to"`-l-.'

er than the negative number regardless of the relative absolute or numerical magnitudes of the two numbers. V

Thus in each row of the table where the values of S `and Sb differ, the value for Ca ently of the value for Cn and Sa is l, and conversely as a l when Sa is-O. This leaves for vdetermination the value for Ca when both input Anumbers are negative, i.e., when both Sa and VSbl have values of 1. l

Since in the complemented-magnitude representation of algebraic numbers, a negative number is represented by the complement of 'the absolute magnitude of the numb'er, two negative numbers of dissimilar absolute magnitude will have a true relative numerical magnitude opposite in sense to Ithe relative numerical magnitude indicated by signalCn. `However, since the true algebraic relative magnitude vof two negative numbers is opposite in'sense to the relative numerical" magnitude of the numbers, the truev algebraic relative magnitude `of the two numbers is directly indicated by the value of signal Cn. negative number A is greater than the absolute magnitude -of a second negative number B, then a comparison is determined independis inserted as a 0 when of the complements fof the numbers will indicate that the absolute magnitude of iB is greaterthany A as indicated by a 0 value for 1Since -both A and B are negative, however, the lnumber Bhas axtrue algebraic magnitudev greater than the number A, which' s represented by-a 0 value for Ca. In each ca'se when both Sa and Sb .are `1 in :the table, therefore, the value for Ca is inserted as .equal to the vcorresponding value lfor Cn. y y From TablelII above,..'function for Ca lmay lbe Written as follows: v f

1 Ca=Cn.(Si-|Sb)+n.a.Sb

Reference is now made to Fig. 4, where there is schematically presented a parallel algebraic comparator 40 mechanized according to thek yabove principles for comparing algebraic numbers A and B, represented by numerical'binary signals A1, Aj, An and Bj', Bn; respectively; and sign signals Su andfSb, respectively. As shownin :braic comparator 40 comprises an `absolute magnitude comparison circuit 40Cn which'produces binary signals Qn asa f unction fof signals VA1, A5, -Angand nl, 13 parison circuit ;40Ca which; .receives signals Cn and the sign signals Sa and Sb and produces a binary signal Ca representing Ethe true algebraic relationship ofpnumbers Advand B. l Y h -It gwill .be 4noted that the absolute `magnitude comparison circuit 40Cn is similar to the absolute .magnitude comparison vcircuit 20Cn of Fig. 2 in that it is comprised Thealgebraic comparison circuit 40Ca is mechanized in accordance with the following logicalexpression'for :Ca

ySince the above expression requires the complement .-n

no further detailed discussion of Fig. 4 isvcwonsidered necessary.

Ifthe corresponding numerical binary digits of num- :bers -A' and B are serially compared in the order of `de-V scending weights or significance, thenl the logical expres- I above, will no longer 'be dependent upon the sion for Cj, derived from Table apply since the value `of Cj will first dissimilar corresponding numerical digits compared. .In 'order'to .obtain a function for C3 under these conditions, an inhibitingiterm must be incorporated in the function for Cj which will inhibit comparisons following tle"'iirst dissimilar corresponding numerical digits compared.V If a binary signal I is in a ,l-representing state when the most significant dissimilar correspondingl binary digits of numbersfA and B indicate that A is numerically less than B, and in a O-representing state under l all other conditions, the .function 'interms of-v its4 previous value, binary digit place, as follows:

'Cj=Cj 1-`|Aj.j. i l If the signs are received after the numerical digits of the numbers are compared, the 'function forffthefalgebraic relative magnitudes, Cf, of A and B, may be obtained by logically adding the` term SaSb, indicating that A 'is ,positive vand Bnega'tive, `the signs of the numbers preceder theY numerical digits,

for Cj maybe expressed the figure, the 'alge- I' Bn, andan algebraic magnitude com- 1 discussions on the mecha- Cj 1, 1n the precedingl to 'the above expression. When vas a function of the binary numerical magnitude representation. `the 'invention have been lill the inhibiting term, I, must be expanded to include the term SLLSb, thus giving the expression:

vfor-the inhibiting term I; and the function for Cja then becomes: v l

Cja=Cj 1+S.Sbij-Bjl ing reception of the numerical digits of numbers A and B, and'is a O-representing signal during reception of the sign signals of the numbers.-

Reference is now made to Fig. 5 wherein there is presented an algebraic comparator 50 for serially determining and indicating the relative magnitudes of two algebraic numbers A and B represented, respectively, by binary input signals Aj, j, and Bj, Bj; each number being received in the order of sign signal rst and least signiicant numerical digit signal last. As shown in the figure, the comparator 50, in response to signals Aj, j, Bj, and Bj, sign' signals StLb and aSb produced by a sign signal circuit 5l, a reset binary signal R, and a synchronizing pulse Cp, produces a pair of binary control signals lCja and OCj*l representing the relative magnitudes of the algebraic'numbers A and B. The sign signals SzLSb and SzLSb are produced by the sign circuit S1 as a function of the Aj, 'j, Bj, Bj signals and a sign position signal Ps which is in a l-representing state during reception of sign indicating binary signals Aj, Aj, Bj Bj, and in a O-representing state during reception of numerical digit representing Aj, j, Bj Bj, signals. The comparator 50 includes an absolute magnitude comparison circuit 50Cn which produces a pair of binary numerical comparison signals, in response to the Aj, Aj, Bj, Bj, and '15s signals, and an algebraic comparison circuit SGCa which produces the binary control signals lCj'L and OCja comparison signals, ysign signals Sa.S'b and SoLSb, reset signals R, and the synchronizing pulses Cp. It is noted that the output element 12 of `Fig. l is herein presented as a ip-iiop (stica) C having 1 and 0 input circuits responsive to lCja and Cj Signals, respectively.

' The absolute magnitude comparison circuit 50Cn `is similar to the absolute magnitude comparison circuit 30Cn of Fig. 3, and needs no further explanation. The algebraic comparison VSOCa, which includes a ip-op I having 1 and 0 input circuits responsive'to a pair of control signals 1I and 0l, respectivelyis mechanized in accordanceV with the logical mechanization Equations 50Ca above, and in light of previous discussions Aonthe mechanization of logical equations, further explanation is deemed unnecessary. A 'j From the foregoing discussion it is `apparent that lthe present invention provides an algebraic comparator for directly determining and indicating the relative magnitudes of two algebraic numbers represented by two sets of binary digit signals. Species of the invention have been dcribed in detail for directly determining and indicating.; the relative magnitudes of numbers in, a signabsolute-magnitude representation and a .complemented ln addition, embodiments of described in detail for both lparallel and serial operation. Although theserial embodiments of the present inventiondes'cribedin detail have been operable upon algebraic numbers received in two sequences or orders, that is', least significant numerical digits first and sign last, and `signs rst and least signiicant numerical digits last, it will be understood that a considerable variety of serial mechanizations are possible. For example, other serial embodiments .described may be utilized, with minor changes, in a system-'wherein each algebraic number is received in the order of most signiicant numerical digit first and sign last, -or sign first and most signicant numerical digit last, either in a signabsolute-magnitude or complemented-magnitude representation. It should also be understood that although the serial and parallel embodiments of the present invention have been described as operating in a sign-absolutemagnitude and complemented-magnitude representation, the algebraic comparator of the present invention is readily adaptable to any algebraic number system whereinthe signs of the algebraic numbers are discernible by binary signals. v

Although the present invention has been described in relation to binary electrical pulses, it should be apparent that the principles herein taught are equally applicable to any two-condition signal system such as mark space, symmetrical wave, or carrier modulation system. It should be further apparent that the present invention is not limited to purely binary number systems but is equally operable with any binary-digit coded system such as the binary-coded decimal system, the binary-coded octal system, and the like. l

The embodiments herein described utilize electrical signals, electrical gates, and electronic flip-Hops, butit should be clearly understood that the principles herein taught are equally applicable to electro-mechanical, mechanical, hydraulic, or chemical components having unidirectional features, two stable states, and storage capacity.

What is claimed as new is:

l. A comparator for receiving two pluralities of input signals representing the complemented magnitudes of two negative algebraic numbers and representingthe negative signs of the two numbers and forA producing an output signal indicating the relative magnitudes 'of the numbers, including, numerical comparison means including a plurality of and and or networks connected in aparticular interrelationship for response to the numerical signais in the iirst and second series to produce a iirst plurality of signals representing the comparison of successive digits in the numbers and to produce the 'comparison signals for each particular digit in accordance with the comparison provided for the previous digit and the values of the input numbers for the particular digit and to produce aA control signal representing Athe results ,of the numerical comparison in the successive digits of the numbers, and algebraic comparison means coupled to said numerical comparison means and including a plurality of and and or networks connected in a particular interrelationship for response to saidfsignals from said numerical comparison means and to the signals representing the negative signs of the input numbers to produce an output signal indicating the relative algebraicmagnitudes of the two numbers directly in accordance with the characteristics of said control signal.

2. A comparator for serially receiving two pluralities of input signals'representing the magnitudes of two algebraic numbers and representing the algebraicsigns of the two numbers and for producing an output signal representing the relative algebraic magnitudes of the numbers, comprising: input signal circuits for serially lpresent- 'ing the input signals representing the magnitudes ot the n al circuits 'and said timing signal circuits for producing sign signals dur-ing 'the'peri'od of presentation of said 'sign timing signals, numerical comparison means coupled to said input signal circuits and to said timing signal circuits and including a plurality of and and I-or" networks 'connected in a particularinterrelationship for re- 'sponse =to said number timing signalsand to successive input signals representing corresponding ymagnitudes in each ofthe Anumbers, algebraic comparison means coupled 'to' said numerical comparison means and to said sign -signal circuits and including a plurality of and and or vnetworks f connected in a particular interrelationship for response to signals from said numerical comparisonj means during .the period of presentation of said number timing signals and for response to said sign signals iduring the yperiod of presentation 'of said -sign timingr signals, an electrical storage device controllable between two electrical states andfcoupledto said algebrai'c 'comparison' meansrand controlled by the output signals therefrom, 'said-storage device being controlled by output 'signals from Vsaid numerical comparison: means during the periodV of said number timing signals vand being controlled in accordnce with said sign signals during the periodof 'said sign timing signal. f f

3.`A comparatorfor serially receiving two ,'pluralitie's of inputA signals representing the magnitudes of two al.- gebraic numbers and representing the algebraic 4signs of the two numbers and for producing an output signal representing the relative algebraic magnitudesl of the numbers, comprising: input signal circuits for serially present- -ing the Vinput signals representing thev magnitude o f the numbers in thev order of decreasing,signiicance'and for presenting the in'p'ut signals represen-tingthe signs ofthe numbers, timing' signal circuits presenting numbertiming signals during ftheperi'od 'of presentation of the input sig- -nals representing-'the magnitudes-V of; thenumbers and .presenting sign timing signals during the period of presentation `ofy the inputsignals represent-ing' the "signs of the Vnumbers sign signal circuits coupled to said input signal circuits" andto saidl timing signal circuits for producing Sign signals during the period 4ofpresentat-ion of said sign `timing signals, numerical-comparison means coupled to sa-id input'signal` circuits and saidtiming signal circuits and including a plurality-of and and or networks connected in a particular interrelationship for'response to said number timing signals land to successiveinputsignals representing corresponding digits in each of the numbers, algebraic comparisonl means coupled to said numerical comparison means and to said sign signal circuits', and including a plurality of and and or networks connected in a particularinterrelationship for response to signals from said numerical comparison means during the period of presentation of said number timing signals and for respovnse to said signsignals duri-ng the period of presentation ofk said signltiming signals, an electrical storage device controllable between two'electfrical states and coupled toV said algebraic comparison means and controlled by signals therefrom, land means forming a `part of saidfalgebraic comparison means for inhibiting theyproduct'ion of output signals thereat upon the occurrence of differences in the input signals indicating diierefnces in the magnitudes ofthe numbers at any digitpositiony v 44. A comparator for serially receiving '-two pluralities of input 'signalsV representing the Vmagnitudes, of t'wo al-l gebraic numbers and Vrepresenting the algebraic signs of 'the'two numbers and for producing an'. output signal `representing the relative algebraic magnitudes ofthe numbers, each plurality of signals 'sequentially indicating theV 'absolute magnitude of the number and including lat least one 'signal indicating 'the sign of fthe number, the combination comprising: 'input signal circuits for serially presenting the signals representing the magnitudes of the f numbers and -for presenting at 'least one .input signal representing lthesigns of 'the numbers, timing signal circuits lpresenting number :timingsigna-ls "during the presental*14 t-ion of the input signals representingthe magnitudes of the numbers and 'presenting sign timing signalsfduring the presentation ofthe input signals representing the signs of the numbers, sign signal circuits coupled to said input signal circuits and to said timing signal circuits for producing sign signals during the period of said sign timin'g signals, numerical comparson means including a plurality of and and orv networks connected ina particular interrelationship for response to said number timing signals and to successive input signals representing corresponding digits in each ofthe numbers, algebraic comparison' means coupled to said numerical comparison means and to said sign signal circuits and including a plurality of andan d or networks 'connected 'ina particular interrelationship for response to signals from said numerical comparisonmeans during the period of said number timing signals and for response to said sign signals during the period of presentation of said sign' timing signals and producing .a rst output signal upon the occurrence during the lnumber timing signals of a signal from said numerical comparison means representing digits of greater magnitude for one linput number than fork the other input number or upon the occurrencejof aiirst sign signalA for a particular one of the' input numbers during the presentation of the sign timing signal, and for the production'of a second output signal upon the oc- 'curren'ce during the number timing signal of a signal `from saidnumerical comparison means representing digits of a greater magnitude for said other input number than for 'said one input number or upon the 'occurrence of the rstsign signal for said other input number during thepresentation of the sign timing signal, and an electrical storage device controllable between two electrical states and'coupled to 'said algebraic comparison means and corrtrolled output signals therefrom. Y

mented magnitudes of eitheror both of the numbers and input signalsrepresenting the signs ofthe numbers, timing signal circuits presenting number timing signals during the presentationeof the input signals representingth'e numbers and 'for producngysign timing signalsdurng the presentation of the? input "signals-representingthe signs of the numbers, sign signalV circuitscoupled tosa-idl input signal circuits andto Saidtiming signal circuits for producing sign signals 'during' -the periodof presentation of said sign `timing signals, numerical comparison means connected to'sai'd input signal circuits and'to said timing signal circuits and including 'a plurality' of and and or networks connected in 'a particular interrelationship for response to saidnum'ber tim-ing signals and to successive input signals representing corresponding digits in each of the numbers, algebraic comparison means coupled vto f said numerical comparison means and to said signfsignal circuits land including a plurality of and and or networks connected in a particular interrelationship for respon'se to signals from vsaid numerical comparison means' during the period of said number timing signals and for response to said sign signals during lth'e period of said sign timing signals, 'said algebraic comparisonscircuit producing a first output signal upon 'the simultaneous occurrence of signals representing digits of different magnitudes during the number timing signals, or upon the occurrenee of sign signals rrepresenting number signs of opposite yalgebraic: signicance during'th'ei-sign timing' signals, an electrical storage device controllable between two electrical states and normally being in one lof said'fftwo electrical states, said electrical storage device being coupled to said algebraic comparison means and being controlled to the other of said two electrical states by said first output signal, and electrical means coupled to said electrical storage device for applying a reset signal thereto to restore said device to said one electrical state.

6. A comparator for serially receiving two pluralities of input signals representing the magnitudes of two algebraic numbers and representing the algebraic signs of the two numbers and for producing an output signal representing the relative algebraic magnitudes of the numbers, comprising: input signal circuits for serially presenting the input signals representing the signs of the numbers and thereafter presenting the input signals representing the magnitude of the numbers in the order of decreasing significance, timing signal circuits presenting number timing signals during the period of presentation of the input signals representing the magnitudes of the numbers and presenting sign timing signals during the period of presentation of the input signals representing the signs of the numbers, sign signal circuits coupled to said input signal circuits and to said timing signal circuits for producing sign signals during the period of presentation of said sign timing signals, numerical comparison means coupled to said input signal circuits and said timing signal circuits and including a plurality of and and or networks connected in a particular interrelationship for response to said number timing signals and to successive input signals representing corresponding digits in each of the numbers, algebraic comparison means coupled to said numerical comparison means land to said sign signal circuits and including a plurality of and and or networks connected in a particular interrelationship for response to signals from said numerical comparison means during the period of presentation of said number timing signals and for response to said sign signals during the period of presentation of said sign timing signals, an electrical storage device controllable between two electrical states and coupled to said algebraic comparison means and controlled by signals therefrom, and means forming a part of said algebraic comparison means for inhibiting the production of signals by said algebraic comparison means in response to signals from said numerical control means during the period of said number timing signals and upon the occurrence of a particular interrelationship between the sign signals for the numbers during the period of presentation of said sign timing signals.

7. A serial comparator for receiving two series of input signals each having a plurality ott sequential signals indieating the magnitude of the number and at least one signal indicating the sign of the number, including, means for providing first timing signals during the occurrence of the sequential signals representing the magnitudes of the input numbers and for providing second timing signals during the occurrence of the sign signals for the numbers, first comparison circuitry connected to the timing means for activation during the first timing signals and responsive to the sequential input signals during its activation to produce control signals in accordance with the occurrence of particular patterns in the successive input signals, and second comparison circuitry connected to the first comparison circuitry and to the timing means for the production of an output signal upon the occurrence of particular control signals during the first timing signals or upon the occurrence during the second timing signals of particular patterns of the signals Irepresenting the signs of the input numbers.

8. The comparator set forth in claim 7 in which the first comparison circuitry is connected to produce first control signals upon the simultaneous occurrence of input signals representing digits of opposite polarity for the input numbers during the first timing signals or upon the occurrence of the first control signals from one digital position and the simultaneous occurrence during the first timing signals of the first signal for one of the input l@ numbers in the next digital position or of a signal representing an opposite polarity for the other input number in the next digital position and is connected to produce second control signals at other times during the first timing signals.Y

9. The comparator set forth in claim 8 in which the sequential input signals represent the absolute magnitudes of the input numbers and in which the second comparison circuitry is connected to produce a rst output signal upon the Voccurrence of the first control signals during the first timing signals or upon the occurrence of sign signals of the first polarity fora particular one of the input numbers during the second timing signal and is connected to produce a second output signal upon Vthe occurrence of second control signals during the first timing signals or upon the occurrence of signsignals of the particular polarity for the other input number'du'ring the second timing signals.

10. The comparator set forth `in claim 8 in which the sequential input signals represent the complemented magnitudes of the input numbers and in which the second comparison circuitry .is connected to produce a first output signal upon the occurrence during the first timing signals of signals representing digits of opposite polarity for the input numbers or upon the occurrence of signals representing signs of opposite polarities for the two input numbers during the second timing signals and is connected to produce a second output signal at other times.

11. A parallel comparator forreceiving first and second pluralities of input signals each having a first plurality of signals indicating the magnitude of the number and at least one signal indicating the sign of the number and wherein each of the pluralities of input signals indicate the complemented magnitude of the number for a negative value ofthe represented number,l including, a numerical comparator including a plurality of stages each connected to vproduce an output signal and each" stage except the first including at least one and network and at least one or network connected to operate vill-a particular interrelationship for the production of a first output signal upon the occurrence of signals representing different values for the particular digits in the input numbers or upon the occurrence of a first output signal from the previous stage in the comparator and the -occurrence of an input signal representing the first value ifor the particular digit vof a first one of the input numbers or of an input signal representing an opposite value for the particular digit of the other input number, and a sign comparator including at least one and network andV at leastv one or network and connected to the numerical comparator to receive the output signal from the cornparator and connected to receive the signals representing the signs of the input numbers and connected to operate on the received signals in a particular interrelationship to produce a first output signal upon the occurrence of a signal representing a first comparison from the numerical comparator and a signal representing a first sign for the second input number or an opposite sign for the first input number, or upon the occurrence of signals representing a second comparison from the numerical cornparator, the first sign for the second inputnumber and the second sign for the first input number, said output signals of said sign comparator representing the comparison between the two input numbers. i

l2. An algebraic comparator for receiving two algebraic numbers A and B represented by two series of complementary numerical binary signals A, and B, respectively, and complementary sign binary signals Sa, Sa, and Sb, Sb, respectively, and producing an output signal corresponding to a signal Ca representing the algebraic relative magnitudes of numbers A and B, said comparator comprising: numerical comparison means responsive to signals A, B, and for producing absolute magnitude signals corresponding to a signal Cn representing the numerical relative magnitudes of algebraic numbers A and B; and algebraic comparison means coupled to said numerical comparison means and responsive to said Cn signal and signals Sa, Sa, Sb, and Sb for producing said output signal.

13. The algebraic comparator delined in claim l2 wherein the algebraic numbers A and B are in signabsolute-magnitude representational form and wherein said signal Ca is defined by the logical equation:

where the presence of a bar over a signal indicates that it is the complement of the signal, and where a dot represents the logical and, and a plus the logical on 14. The algebraic comparator defined in claim 12 wherein numbers A and B 'are in complemented-magma tude representational form and wherein said signal Ca is deiined by the logical equation:

where the presence of a bar over a signal indicates that it `is the complement of the signal, and where a dot represents the logical and, and a plus (l) the logical on 15. The algebraic comparator defined in claimjjlZ wherein said numerical comparison means produces an absolute magnitude signal Cj for each corresponding binary-digit place of numbers A and B, the value of signal Cj for the highest order binary-digit place representing signal Cn, each signal Cj being produced as a function of corresponding numerical signals Aj, Bj, and a signal Cj- 1 representing the value of signal Cj for the neXt lower order binary-digit place, in accordance with the logical equation:

Cf=iBi+Ci-1(Arl-Bi) where the presence of a bar over a signal indicates that it is the complement of the signal, and where a dot represents the logical and, iand a plus the logical or.

16. The algebraic comparator defined in claim 12 wherein each of said series of numerical and sign signals are serially received by said comparator and wherein said comparator further includes a bistable output elevment having l-setting and (.)-setting input circuits 1Ca and OCa, respectively, for assuming a nal stable state representing signal Ca.

17. The algebraic comparator defined in claim 16 wherein the numbers A and B are received in sign-absolute-magnitude representational form and are received in the order of corresponding least significant numerical signals first and sign signals last, wherein input circuits lCa and OCa of said bistable element are responsive to absolute magnitude signals A. and .B, respectively, for

assuming a stable state representing signal Cn, wherein input circuits lCa and OCa are responsive to output signals Sa and Sb, for assuming a final stable state representing signal Ca, and wherein said lCa and OCa input circuit signals are definable by the logical equations:

where the presence of a bar over a signal indicates that it is the complement of the signal, and where a dot represents the logical and, and a plus the logical on 18. The algebraic comparator defined in claim 16 wherein the algebraic numbers A and B are received in complemented-magnitude representational form and are received in the order of corresponding sign signals first and corresponding least significant numerical signals last, and wherein said algebraic comparison means includes inhibiting means responsive to absolute magnitude signals .B and sign signals Sa and Sb for producing an inhibiting signal I in accordance with the logical function:

where the presence of a bar over a signal indicates that it is the complement of the signal, and where a dot represents the logical and, and a plus the logical on 19. The algebraic comparator defined in claim 18 wherein said inhibit means includes a bistable storage element responsive to signal I and producing complementary voltage-level signals I and and wherein said algebraic comparison means further includes an output means responsive to absolute magnitude signals A, sign signals Sa and Sb, and a reset signal R for producing output signals lCa and OCa for application to said lCa and OCa input circuits, respectively, of said bistable output element, said output signals being produced in accordance with the logical equations:

where the presence of a bar over a signal indicates that it is the complement of the signal, and where a dot represents the logical and, a plus the logical or.

References Cited in the file of this patent UNITED STATES PATENTS 

